library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ImageCorrection is
  port( DataIn : in std_logic_vector(9 downto 0);
        Clk : in std_logic;
        Row : in std_logic_vector(8 downto 0);
		  Col : in std_logic_vector(9 downto 0);
        DataOut : out std_logic_vector(9 downto 0));
end ImageCorrection;

architecture corr of ImageCorrection is

	component rom IS
		port (
			clka: IN std_logic;
			addra: IN std_logic_VECTOR(9 downto 0);
			douta: OUT std_logic_VECTOR(15 downto 0));
	END component;

  signal input,add,output : std_logic_vector(9 downto 0):="0000000000";
  signal value : std_logic_vector(15 downto 0);
  signal r : std_logic_vector(8 downto 0);
  signal c : std_logic_vector(9 downto 0);
  
begin

	CorrData: rom port map(clk,c,value);
  
  r<=Row;
  c<=Col;
  
  process(clk,DataIn,add,input,output)
  begin
	 if rising_edge(Clk) then
		 input<=DataIn;
		 add<=value(9 downto 0) + input;
		 output<=add;
		 DataOut<=output;
	 end if;
  end process;
  
end corr;